1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a nonvolatile, NAND-type flash memory and a manufacturing method thereof.
2. Description of the Related Art
Among nonvolatile memories capable of storing and erasing data electrically, a NAND-type (electrically erasable and programmable read only memory) EEPROM has a unit cell generally constructed of a laminated structure of a floating gate and a control gate.
A unit string is comprised of a string selection transistor (SSL) for selecting a bit line, a plurality of unit cells having a laminated structure of a floating gate and a control gate, a ground selection transistor (GSL) for selecting a common source line (CSL), the sources and drains of which are connected in series to a plurality of bit lines and word lines, and the common source line CSL. A plurality of unit strings are connected in parallel to the bit lines. A conventional NAND-type EEPROM was disclosed in an article entitled xe2x80x9cA 4-Mbit NAND EEPROM with tight programmed Vt Distributionxe2x80x9d pp. 105-106, Symposium in VLSI Circuits held in 1990.
FIG. 1 is a cross-sectional view of a conventional NAND type EEPROM cell, in the bit line direction. A n-type well 53, being of a second conductivity type, is formed on a p-type semiconductor substrate 51, which is of a first conductivity type. A p-type pocket well 55 is formed within well 53. A string selection transistor (SSL) 57 and unit cell 59 are formed on semiconductor substrate 51, on pocket well 55. An insulating layer 61 and a bit line pattern 63 are formed over SSL 57 and unit cell 59, respectively. In FIG. 1, reference numeral 65 represents the floating gate of a transistor forming a unit cell next to unit cell 59, and reference numeral 67 represents the control gate which is a word line. Reference numeral 69 represents a channel area formed in the semiconductor substrate.
FIG. 2 illustrates an equivalent circuit 76 of the NAND-type EEPROM cell and a table 78 showing its operational characteristics during programming, erasing and reading operations. In circuit 76, reference character A represents a cell selected during a programming operation, and reference character C represents a unit string.
However, according to the conventional art, insufficient field isolation between a unit cell and its neighboring unit cell, which is due to high integration of a nonvolatile memory device, results in leakage current due to a high word line voltage Vpgm used in programming a cell. Thus, a disturbance phenomenon, also known as cross talk, where a cell (B of FIG. 2) adjacent to a selected cell (A of FIG. 2) for being programmed is also programmed, may occur.
Also, a problem appears in the manufacturing process. According to the method for forming the unit cell shown in FIG. 1, in order to prevent misalignment of the floating gate and the control gate, a self-align etching process, in which the control gate and the floating gate are simultaneously etched, is performed using the same etching mask. However, in the course of the etching process, to prevent formation of stringer by which the floating gates of adjacent cells in the bit-line direction are shorted by a field oxide layer in which polysilicon is not present, over-etching may be performed, which makes the field oxide layer thin. Although not shown in FIG. 1, the field oxide layer is formed vertically with respect to the control gate and the floating gate and parallel with the bit line. Thus, during a subsequent ion implantation process for source/drain regions, ion impurities for forming a source and a drain are implanted into the lower portion of the thinned field oxide layer, and as a result field isolation characteristics in this region are deteriorated.
Since field isolation characteristics in this region are deteriorated, electrical insulating capability from adjacent unit cells is lowered during memory device operation, thus causing malfunction of the cell.
To solve the above problems, it is an objective of the present invention to provide a programming operation by greatly improving a coupling ratio by increasing the capacitance of an interpoly dielectric layer between a floating gate and a control gate while reducing the area of the unit cell, and with a reduced thickness field oxide layer by avoiding etching loss caused by over-etching of the field oxide layer, while etching the floating gate and the control gate without misalignment.
It is another objective of the present invention to provide a NAND-type flash memory unit cell with reduced operational voltage during a programming operation by greatly improving the coupling ratio by increasing the capacitance of an interpoly dielectric layer between a floating gate and a control gate while reducing the area of a unit cell, and with a reduced thickness field oxide layer by eliminating etching loss caused by over-etching of the field oxide layer while etching the floating gate and the control gate without misalignment.
It is still another objective of the present invention to provide a method for manufacturing the NAND-type flash memory including the unit cell.
To achieve the first two objectives, flash type programmable nonvolatile memory unit cells are provided. Each unit cell is formed such that the interpoly dielectric layer and the control gate surround the top surface and also the four lateral surfaces of the floating gate. This increases the capacitance between the floating gate and the control gate, which improves a coupling ratio. This also improves electromagnetic shielding within each cell, which reduces cross talk between neighboring cells, and permits more dense integration.
More specifically, to achieve the above first objective, there is provided a programmable nonvolatile memory unit cell formed at the intersection of a bit line and a word line, including source/drain regions of a second conductivity type, formed on a semiconductor substrate of a first conductivity type on which a field oxide layer is formed, a first insulating layer formed on a channel area between the source/drain regions; a floating gate formed on the first insulating layer, a second interpoly dielectric layer surrounding the top surface of the floating gate, and four lateral surfaces in the word line and bit line directions, and a control gate surrounding the top surface and four lateral surfaces of the second interpoly dielectric layer.
To achieve the second objective, there is provided a NAND-type flash memory unit cell formed at the intersection of a bit line and a word line, including source/drain regions of a second conductivity type formed on a semiconductor substrate of a first conductivity type on which a field oxide layer is formed, a first insulating layer formed on a channel area between the source/drain regions, a floating gate formed on the first insulating layer; a second interpoly dielectric layer surrounding the top surface of the floating gate, and four lateral surfaces in the word line and bit line directions, and a control gate surrounding the top surface and four lateral surfaces of the second interpoly dielectric layer.
In both cases, the second interpoly dielectric layer may employ one-layer material, or two-layer materials comprised of a second insulating layer surrounding the top portion of the floating gate and two lateral surfaces in the bit line direction, and a third insulating layer surrounding two lateral surfaces in the word line direction.
To achieve the third objective, there is provided a method for forming a NAND-type flash memory device. A first word line pattern is first formed by depositing a first polysilicon layer, a first interpoly dielectric layer and a second polysilicon layer on a semiconductor substrate on which a field oxide layer is formed, in a vertical direction with respect to the field oxide layer and the same is patterned. A spacer insulating layer is formed on both sides of the first word line pattern. Then, a planarizing insulating layer is deposited over the entire surface of the semiconductor substrate having the spacer insulating layer and planarizing the same to expose the surface of the second polysilicon layer on the first word line pattern. The second polysilicon layer is partially etched to partially expose the first interpoly dielectric layer of the first word line pattern on the field oxide layer. The first polysilicon layer is partially exposed by partially etching the exposed first interpoly dielectric layer. The exposed first interpoly dielectric layer is partially etched and the second polysilicon layer is entirely etched. An independent floating gate is formed by etching the first interpoly dielectric layer exposed by etching the second polysilicon layer from the resultant structure, and the spacer insulating layer. A second interpoly dielectric layer is formed on top of and at four lateral surfaces of the floating gate. A second word line pattern is formed by depositing a conductive layer to be used as a control gate on the resultant structure having the second interpoly dielectric layer and the same is patterned in the word line direction.
According to a preferred embodiment, after the field oxide layer is partially exposed and the oxide layer is filled in the exposed region of the first polysilicon layer into which the first conductivity type impurity is ion-implanted, the second interpoly dielectric layer is formed, thereby improving field isolation capability.
According to the present invention, the coupling ratio is improved by increasing the capacitance of the second interpoly dielectric layer between the floating gate and the control gate, thereby reducing the operational voltage of a nonvolatile memory device. Therefore, the field isolation voltage between unit cells is reduced due to the reduced operational voltage, and the area of a unit cell is reduced by decreasing the thickness of the field oxide layer, hereby attaining high integration.